The invention relates to dynamic random access memory (DRAM).
Random access memory (RAM) falls generally into two categories, namely, static and dynamic. Both types of RAM are made up of an array of addressable storage cells, each one storing a bit of information (or multi-bit information). In static RAM (SRAM), the storage unit within the cell is typically a bi-stable flip-flop and the state of the flip-flop indicates whether the cell stores a zero or a one. In dynamic RAM (DRAM) the storage unit is typically an IC capacitor and the charge on the capacitor indicates whether the stored value is either a zero or a one. In the case of DRAM's, however, capacitors gradually lose charge and thus it is necessary to "refresh" the stored data as often as every few milliseconds (though in more recent DRAM that has been increased to on the order of hundreds of milliseconds and even seconds). The refreshing operation is performed by first reading the value in the cell and then writing it back. This is done for every cell in the array and it typically requires complicated control circuitry.
The earliest DRAM cell, introduced in the early 70's, contained four transistors. Later, 3-transistor DRAM cells were introduced, which made the cell size smaller and memory density higher. Shortly after, the 1-transistor/1-capacitor cell was introduced, which wiped out all its competitors because of its simplicity as well as its small cell size, and has remained an industry standard. Over the years, through the 4K, 16K, 64K, and 256K DRAM generation, the cell size was reduced by shrinking both the transistor and the capacitor dimensions, and it was easier to shrink the capacitor than the transistor because of the former's simplicity. Starting from the 1 Mb DRAM generation in the mid 1980's, however, the situation has reversed, because the capacitor has been forced to assume a more and more complicated 3-dimensional structure to live within the "real estate" area allocated for a given cell size. It is safe to say that the most costly part of the DRAM cell, including the R&D efforts and the production cost, is, and will continue to be into the foreseeable future, the capacitor. And it may very well be the show stopper against continued scaling somewhere down the line, unless a new DRAM cell design is adopted which can live without the capacitor.